9DBL09P1 Overview
The 9DBL09x1 devices are 3.3V members of IDT's Full-Featured PCIe clock family. The 9DBL09x1 devices support PCIe Gen1 4 mon Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. They offer a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines.
9DBL09P1 Key Features
- 1-200 MHz Low-Power (LP) HCSL DIF pairs
- 9DBL0941 default Zout = 100Ω
- 9DBL0951 default Zout = 85Ω
- 9DBL09P1 factory programmable defaults
- Easy AC-coupling to other logic families, see IDT
- DIF additive cycle-to-cycle jitter < 5ps
- DIF output-to-output skew < 50ps
- Additive phase jitter is 0p