ICS854S006I - Differential-to-LVDS Fanout Buffer

Product Overview

IDT

Part number	ICS854S006I
Manufacturer	IDT
File Size	188.52 KB
Description	Differential-to-LVDS Fanout Buffer
Datasheet	ICS854S006I Datasheet
Additional preview pages of the ICS854S006I datasheet.

The ICS854S006I is a low skew, high perforICS mance 1-to-6 Differential-to-LVDS Fanout Buffer.

ferential input levels.

The ICS854S006I is characterized to operate from either a 2.5V or a 3.3V power supply.

Six differential LVDS outputs.
One differential clock input pair.
CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL.
Maximum output frequency: 1.7GHz.
Translates any single ended input signal to LVDS levels with resistor bias on nCLK input.
Output skew: 55ps (maximum).
Propagation delay: 850ps (maximum).
Additive phase jitter, RMS: 0.067ps (typical).
Full 3.3V or 2.

ICS854S013 - 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER (Integrated Device Technology)
ICS854S01I - 2:1 Differential-to-LVDS Multiplexer (Renesas)
ICS854S054I - 4:1 Differential-to-LVDS Clock Multiplexer (Renesas)
ICS854S054I - 4:1 Differential-to-LVDS Clock Multiplexer (Integrated Device Technology)
ICS854S057BI - 4:1 or 2:1 LVDS Clock Multiplexer (Integrated Device Technology)
ICS854S058I - 8:1 Differential-to-LVDS Clock Multiplexer (Renesas)
ICS854S058I - 8:1 Differential-to-LVDS Clock Multiplexer (Integrated Device Technology)
ICS854S202I-01 - Differential-To-LVDS Multiplexer (Renesas)
ICS854S204I - LVPECL FANOUT BUFFER (Integrated Device Technology)
ICS854S296I-33 - LVDS Programmable Delay-Line (Renesas)

Other Datasheets by IDT

Published: Dec 21, 2016 |