ICS889832 Datasheet | IDT

DESCRIPTION The ICS889832 is a high speed 1-to-4 Differential IC S to-LVDS Fanout Buffer and is a member of the Hi Per Clock S™ Hi Per Clock S™ family of high performance clock solutions from IDT. The ICS889832 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF _AC pin allow other differential signal families such as LVPECL, LVDS, and SSTL to be easily interfaced to the input with minimal use of external ponents. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889832 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in spaceconstrained applications. FEATURES - Four differential LVDS outputs - IN, n IN pair can accept the following differential input levels: LVPECL, LVDS, SSTL - 50Ω internal input termination to VT - Output frequency: >2GHz - Output skew: 25ps (maximum) - Part-to-part skew: 200ps (maximum) - Additive phase jitter, RMS: <0.2ps (typical) - Propagation delay: 510ps (maximum) - 2.5V operating supply - -40°C to 85°C ambient operating temperature - Available in both standard (Ro HS 5) and lead-free (Ro HS 6) packages BLOCK DIAGRAM Q0 n Q0 IN 50Ω PIN ASSIGNMENT n Q0 Q1 1 n Q1 2 Q2 3 16 15 14 13 12 11 10 9 5 Q3 Q0 IN VT VREF_AC n IN Q1 n Q1 50Ω n Q2 4 6 n Q3 VT n IN Q2 VREF_AC EN D Q n Q2 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View Q3 n Q3 IDT ™ / ICS™ LVDS FANOUT BUFFER ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 4 5, 6 7, 14 Name Q1, n Q1 Q2, n Q2 Q3, n Q3 VDD Type Output Output Output Power Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels....