IDT7007S
Overview
- True Dual-Ported memory cells which allow simultaneous reads of the same memory location
- High-speed access - Military: 25/35/55ns (max.) - Industrial: 20/25/35/55ns (max.) - Commercial: 15/20/25/35/55ns (max.)
- Low-power operation - IDT7007S Active: 850mW (typ.) Standby: 5mW (typ.) - IDT7007L Active: 850mW (typ.) Standby: 1mW (typ.)
- IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device
- M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave
- Interrupt Flag
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- TTL-compatible, single 5V (±10%) power supply
