IDT71V2577S Overview
The IDT71V2577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V2577/79 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture).
IDT71V2577S Key Features
- 7.5ns up to 117MHz clock frequency mercial and Industrial
- 8.0ns up to 100MHz clock frequency
- 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global
- Boundary Scan JTAG Interface (IEEE 1149.1 pliant) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP)