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IDT71V67702 - (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect

General Description

The IDT71V67702/7902 are high-speed SRAMs organized as 256K x 36/512K x 18.

data, address and control registers.

There are no registers in the data output path (flow-through architecture).

Key Features

  • x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times:.
  • 7.5ns up to 117MHz clock frequency.
  • 8.0ns up to 100MHz clock frequency.
  • 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin p.

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Datasheet Details

Part number IDT71V67702
Manufacturer IDT
File Size 540.14 KB
Description (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect
Datasheet download datasheet IDT71V67702 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com 256K X 36, 512K X 18 IDT71V67702 3.3V Synchronous SRAMs IDT71V67902 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect Features x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times: – 7.5ns up to 117MHz clock frequency – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA).