Datasheet4U Logo Datasheet4U.com

IDT71V67702 - (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect

Datasheet Summary

Description

The IDT71V67702/7902 are high-speed SRAMs organized as 256K x 36/512K x 18.

data, address and control registers.

There are no registers in the data output path (flow-through architecture).

Features

  • x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times:.
  • 7.5ns up to 117MHz clock frequency.
  • 8.0ns up to 100MHz clock frequency.
  • 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin p.

📥 Download Datasheet

Datasheet preview – IDT71V67702

Datasheet Details

Part number IDT71V67702
Manufacturer IDT
File Size 540.14 KB
Description (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect
Datasheet download datasheet IDT71V67702 Datasheet
Additional preview pages of the IDT71V67702 datasheet.

📁 Similar Datasheet

  • IDT71V67602 - 3.3V Synchronous SRAMs (Integrated Device Technology)
  • IDT71V67802 - 3.3V Synchronous SRAMs (Integrated Device Technology)
  • IDT71V632 - 64K x 32 3.3V Synchronous SRAM (Integrated Device Technology)
  • IDT71V65603 - 3.3V Synchronous ZBT SRAMs (Integrated Device Technology)
  • IDT71V65803 - 3.3V Synchronous ZBT SRAMs (Integrated Device Technology)
  • IDT71V016SA - 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) (Integrated Device Technology)
  • IDT71V124SA - 3.3V CMOS Static RAM (Renesas)
  • IDT71V2546SA - 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs (Integrated Device Technology)
  • IDT71V2548S - 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs (Integrated Device Technology)
  • IDT71V2548SA - 128K x 36/ 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs (Integrated Device Technology)
Other Datasheets by IDT

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com 256K X 36, 512K X 18 IDT71V67702 3.3V Synchronous SRAMs IDT71V67902 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect Features x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times: – 7.5ns up to 117MHz clock frequency – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA).
Published: |