IDT72V3612 Description
The IDT72V3612 is designed to run off a 3.3V supply for exceptionally lowpowerconsumption. Thisdeviceisamonolithichigh-speed,low-powerCMOS.
IDT72V3612 Key Features
- Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions
- Supports clock frequencies up to 83 MHz
- Fast access times of 8ns
- Free-running CLKA and CLKB can be asynchronous or
- Mailbox bypass Register for each FIFO
- Programmable Almost-Full and Almost-Empty Flags
- Microprocessor interface control logic
- EFA , FFA , AEA , and AFA flags synchronized by CLKA
- EFB , FFB , AEB , and AFB flags synchronized by CLKB
- Passive parity checking on each port