IDT72V3653 Datasheet | IDT

.. 3.3 VOLT CMOS Sync FIFOTM WITH BUS-MATCHING 2,048 x 36 4,096 x 36 8,192 x 36 IDT72V3653 IDT72V3663 IDT72V3673 Features - - - - - - - - Memory storage capacity: IDT72V3653 - 2,048 x 36 IDT72V3663 - 4,096 x 36 IDT72V3673 - 8,192 x 36 Clock frequencies up to 100 MHz (6.5 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024) Serial or parallel programming of partial flags Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte) Big- or Little-Endian format for word and byte bus sizes - - - - - - - - - - Retransmit Capability Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Easily expandable in width and depth Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin and functionally patible versions of the 5V operating IDT723653/723663/723673 Pin patible with the lower density parts, IDT72V3623/ 72V3633/72V3643 Industrial temperature range (- 40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM MBF1 Mail 1 Register Port-A Control Logic CLKA CSA W/RA ENA MBA RS1 RS2 PRS Bus Matching Input Register Output Register FIFO1 Mail1, Mail2, Reset Logic RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 RT RTM FIFO Retransmit Logic Write...