IDT72V3662 Datasheet | IDT

.. 3.3 VOLT CMOS Sync Bi FIFOTM 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2 IDT72V3652 IDT72V3662 IDT72V3672 Features - - - - - - - - - - - Memory storage capacity: IDT72V3652 - 2,048 x 36 x 2 IDT72V3662 - 4,096 x 36 x 2 IDT72V3672 - 8,192 x 36 x 2 Supports clock frequencies up to 100MHz Fast access times of 6.5ns Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering data in opposite directions Mailbox bypass register for each FIFO Programmable Almost-Full and Almost-Empty flags Microprocessor Interface Control Logic FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB - - - - Select IDT Standard timing (using EFA, EFB, FFA and FFB flags functions) or First Word Fall Through timing (using ORA, ORB, IRA and IRB flag functions) Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving 120-pin Thin Quad Flatpack (TQFP) Pin and functionally patible versions of the 5V operating IDT723652/723662/723672 Pin patible to the lower density parts, IDT72V3622/72V3632/ 72V3642 Industrial temperature range (- 40°C to +85°C) is available DESCRIPTION The IDT72V3652/72V3662/72V3672 are pin and functionally patible versions of the IDT723652/723662/723672, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, highspeed, low-power, CMOS Bidirectional Sync FIFO (clocked) memories which support clock frequencies up to 100MHz and have read access times as fast FUNCTIONAL BLOCK DIAGRAM MBF1 CLKA CSA W/RA ENA MBA Mail 1 Register Input Register Output Register Port-A Control Logic RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 RST1 FIFO1, Mail1 Reset Logic Write Pointer Read Pointer EFB/ORB AEB FFA/IRA AFA FIFO 1 Status Flag Logic FS0 FS1 A0 - A35 Programmable Flag Offset...