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64Mb (x32) - SDR Synchronous DRAM
2M x 32 bit Synchronous DRAM (SDRAM)
Overview
The 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 67,108,864bits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a Bank Activate command which is then followed by a Read or Write command.
NDS63P Datasheet
