NDS73P Datasheet | INSIGNIS

128Mb (x32) - SDR Synchronous DRAM 4M x 32 bit Synchronous DRAM (SDRAM) Overview The 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 1M x 32 bit banks is organized as 4096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate mand which is then followed by a Read or Write mand. The SDRAM...