IS42S16400C1 Datasheet | ISSI

FEATURES OVERVIEW t a ISSI's 64Mb Synchronous DRAM IS42S16400C1 is - Clock frequency: 166, 143 MHz D organized as 1,048,576 bits x 16-bit x 4-bank for improved . synchronous; all signals referenced to a - Fully performance. The synchronous DRAMs achieve high-speed w clock edge positive data transfer using pipeline architecture. All inputs and w outputs signals refer to the rising edge of the clock input. bank for hiding row access/precharge w- - Internal Single 3.3V power supply - LVTTL interface - Programmable burst length - (1, 2, 4, 8, full page) - Programmable burst sequence: Sequential/Interleave - Self refresh modes ISSI ® - 4096 refresh cycles every 64 ms - Random column address every clock cycle - Programmable CAS latency (2, 3 clocks) - Burst read/write and burst read/single write operations capability - Burst termination by burst stop and precharge mand - Byte controlled by LDQM and UDQM - Industrial temperature availability - Package: 400-mil 54-pin TSOP II - Lead-free package is available PIN DESCRIPTIONS A0-A11 BA0, BA1 DQ0 to DQ15 CLK CKE CS RAS CAS m o .c U 4 t e e h S a t a .D w w w PIN CONFIGURATIONS 54-Pin TSOP (Type II) VDD DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 GND VDDQ GNDQ VDDQ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 DQ9 DQ8 NC GNDQ VDD WE GND LDQM CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 CLK NC A9 A8 A7 A6 A5 A4 CKE A11 VDD GND DQ15 GNDQ DQ14 DQ13 VDDQ DQ12 DQ11 GNDQ DQ10 VDDQ UDQM Address Input Data I/O Bank Select Address LDQM VDD GND VDDQ GNDQ NC UDQM System Clock Input Clock Enable Chip Select Row Address Strobe mand Column Address Strobe mand Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services...