IS42S16400C1 Description
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.
IS42S16400C1 Key Features
- Clock frequency: 166, 143 MHz D organized as 1,048,576 bits x 16-bit x 4-bank for improved . synchronous; all signals re
- Fully performance. The synchronous DRAMs achieve high-speed w clock edge positive data transfer using pipeline architect
- LVTTL interface
- Programmable burst length
- (1, 2, 4, 8, full page)
- Programmable burst sequence: Sequential/Interleave
- Self refresh modes
- 4096 refresh cycles every 64 ms
- Random column address every clock cycle
- Programmable CAS latency (2, 3 clocks)