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IS42S16400C - 64M-Bit x 16-Bit 4 4-Bank SDRAM

General Description

A0-A11 BA0, BA1 I/O0 to I/O15 CLK CKE CS RAS CAS m o .c U 4 t e e h S a t a .D w w w PIN CONFIGURATIONS 54-Pin TSOP (Type II) VDD I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 GND I/O15 I/O14 I/O13 I/O12 I

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IS42S16400Com .c U Bits x 4 Banks (64-MBIT) 64 Meg Bits x4 16 AUGUST 2004 t e SYNCHRONOUS DYNAMIC RAM e h S FEATURES OVERVIEW a t ISSI's 64Mb Synchronous DRAM IS42S16400C is • Clock frequency: 166, 133 MHz a organized as 1,048,576 bits x 16-bit x 4-bank for improved D • Fully . synchronous; all signals referenced to a performance. The synchronous DRAMs achieve high-speed positive w clock edge data transfer using pipeline architecture. All inputs and wInternal bank for hiding row access/precharge outputs signals refer to the rising edge of the clock input. • w• Single 3.