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IS42S16400D - 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

General Description

A0-A11 BA0, BA1 DQ0 to DQ15 CLK CKE CS RAS CAS Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDQM UDQM VDD GND VDDQ GNDQ NC Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask Pow

Key Features

  • Clock frequency: 166, 143 MHz.
  • Fully synchronous; all signals referenced to a positive clock edge.
  • Internal bank for hiding row access/precharge.
  • Single 3.3V power supply www. DataSheet4U. com.
  • LVTTL interface ISSI JULY 2006 ®.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS42S16400 1M-Bit x 16-Bit 4 4-Bank SDRAM ISSI
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IS42S16400A 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM ISSI
IS42S16400B 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM ISSI
IS42S16400B1 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS42S16400 SYNCHRONOUS DYNAMIC RAM
IS42S16400F 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
IS42S16100 512K Words x 16Bits x 2 Banks Synchronous Dynamic RAM
IS42S16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM
IS42S16160 16Meg x16 256-MBIT SYNCHRONOUS DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS42S16400D 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply www.DataSheet4U.com • LVTTL interface ISSI JULY 2006 ® OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S16400D is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.