IS42VM16400K - 1M x 16Bits x 4Banks Mobile Synchronous DRAM
ISSI (now Infineon)
Download the IS42VM16400K datasheet PDF.
This datasheet also covers the IS42SM variant, as both devices belong to the same 1m x 16bits x 4banks mobile synchronous dram family and are provided as variant models within a single manufacturer datasheet.
General Description
These IS42SM/RM/VM16400K are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,567 words x 16 bits.
These products are offering fully synchronous operation and are referenced to a positive edge of the clock.
Key Features
JEDEC standard 3.3V, 2.5V, 1.8V power supply.
Auto refresh and self refresh.
All pins are compatible with LVCMOS interface.
4K refresh cycle / 64ms.
Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst.
Programmable CAS Latency : 2,3 clocks.
All inputs and outputs referenced to the positive edge of the system clock.
Full PDF Text Transcription for IS42VM16400K (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
IS42VM16400K. For precise diagrams, and layout, please refer to the original PDF.
IS42SM/RM/VM16400K 1M x 16Bits x 4Banks Mobile Synchronous DRAM Description These IS42SM/RM/VM16400K are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks...
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are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,567 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features JEDEC standard 3.3V, 2.5V, 1.
IS42VM16400K Datasheet
