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IS45S16400J - SYNCHRONOUS DYNAMIC RAM

General Description

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits.

Internally configured as a quad-bank DRAM with a synchronous interface.

Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits.

Key Features

  • Clock frequency: 200, 166, 143, 133 MHz.
  • Fully synchronous; all signals referenced to a positive clock edge.
  • Internal bank for hiding row access/precharge.
  • Single 3.3V power supply.
  • LVTTL interface.
  • Programmable burst length.
  • (1, 2, 4, 8, full page).
  • Programmable burst sequence: Sequential/Interleave.
  • Self refresh modes.
  • Auto refresh (CBR).
  • 4096 refresh cycles every 64 ms (Com, Ind, A1 grade) or 1.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS45S16400C1 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM Integrated Silicon Solution
IS45S16400E 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM Integrated Silicon Solution
IS45S16400F 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM Integrated Silicon Solution
IS45S16100C1 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM Integrated Silicon Solution
IS45S16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS45S16100F 512K Words x 16 Bits x 2 Banks 16Mb SDRAM
IS45S16100H 16Mb SYNCHRONOUS DYNAMIC RAM
IS45S16160G 256Mb SYNCHRONOUS DRAM
IS45S16160J 256Mb SYNCHRONOUS DRAM
IS45S16160L 256Mb SYNCHRONOUS DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS42S16400J IS45S16400J 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEBRUARY 2022 FEATURES • Clock frequency: 200, 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.