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IS45S32200C1 - SYNCHRONOUS DYNAMIC RAM

Description

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits.

Internally configured as a quad-bank DRAM with a synchronous interface.

Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits.

Features

  • Clock frequency: 143 MHz.
  • Fully synchronous; all signals referenced to a positive clock edge.
  • Internal bank for hiding row access/precharge.
  • Single 3.3V power supply.
  • LVTTL interface.
  • Programmable burst length: (1, 2, 4, 8, full page).
  • Programmable burst sequence: Sequential/Interleave.
  • Self refresh modes.
  • 4096 refresh cycles every 64 ms.
  • Random column address every clock cycle.
  • Programmable CAS l.

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Datasheet preview – IS45S32200C1

Datasheet Details

Part number IS45S32200C1
Manufacturer ISSI
File Size 599.15 KB
Description SYNCHRONOUS DYNAMIC RAM
Datasheet download datasheet IS45S32200C1 Datasheet
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IS45S32200C1 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM ISSI® JULY 2006 FEATURES • Clock frequency: 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.
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