IS45S32200E Overview
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits.
IS45S32200E Key Features
- Clock frequency: 200, 166, 143, 133 MHz
- Fully synchronous; all signals referenced to a positive clock edge
- Internal bank for hiding row access/precharge
- Single 3.3V power supply
- LVTTL interface
- Programmable burst length: (1, 2, 4, 8, full page)
- Programmable burst sequence: Sequential/Interleave
- Self refresh modes
- 4096 refresh cycles every 16ms (A2 grade) or 64ms (mercia, Industrial, A1 grade)
- Random column address every clock cycle