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IS46R83200B - 256Mb DDR Synchronous DRAM

Download the IS46R83200B datasheet PDF. This datasheet also covers the IS43R83200B variant, as both devices belong to the same 256mb ddr synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Vdd =Vddq = 2.5V+0.2V (-5, -6, -75).
  • Double data rate architecture; two data transfers per clock cycle.
  • Bidirectional , data strobe (DQS) is transmitted/ received with data.
  • Differential clock input (CLK and /CLK).
  • DLL aligns DQ and DQS transitions with CLK transitions edges of DQS.
  • Commands entered on each positive CLK edge;.
  • Data and data mask referenced to both edges of DQS.
  • 4 bank operation controlled by BA0 ,.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS43R83200B-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS46R86400D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM Integrated Silicon Solution
IS46R16160F 256Mb DDR SDRAM Integrated Silicon Solution
IS46R16320D 16Mx32 32Mx16 64Mx8 512Mb DDR SDRAM Integrated Silicon Solution
IS46R16320E 512Mb DDR SDRAM Integrated Silicon Solution
IS46R16800E 128Mb DDR SDRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS46R86400F 512Mb DDR SDRAM
IS46R16160B 256Mb DDR Synchronous DRAM
IS46R16160D DDR SDRAM
IS46R16320F 512Mb DDR SDRAM
IS46R32800D DDR SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS43R83200B, IS46R83200B IS43R16160B, IS46R16160B 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM AUGUST 2010 FEATURES: • Vdd =Vddq = 2.5V+0.2V (-5, -6, -75) • Double data rate architecture; two data transfers per clock cycle. • Bidirectional , data strobe (DQS) is transmitted/ received with data • Differential clock input (CLK and /CLK) • DLL aligns DQ and DQS transitions with CLK transitions edges of DQS • Commands entered on each positive CLK edge; • Data and data mask referenced to both edges of DQS • 4 bank operation controlled by BA0 , BA1 (Bank Address) • /CAS latency -2.0 / 2.5 / 3.