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IS61NLF204818A - 36Mb STATE BUS SRAM

Download the IS61NLF204818A datasheet PDF. This datasheet also covers the IS61NLF102436A variant, as both devices belong to the same 36mb state bus sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The 36 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.

Key Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle.
  • Individual Byte Write Control.
  • Single Read/Write control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control us- ing MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Power Down mode.
  • Common data inputs and data outputs.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61NLF102436A-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61NLF204836B FLOW THROUGH (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NLF25632 SRAM Integrated Silicon Solution Inc
IS61NLF25636 SRAM Integrated Silicon Solution Inc
IS61NLF409618B FLOW THROUGH (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NLF51218 SRAM Integrated Silicon Solution Inc

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NLF25618A (IS61NVFxxxxxA) STATE BUS SRAM
IS61NLF25636A (IS61NVFxxxxxA) STATE BUS SRAM
IS61NLF25672 STATE BUS SRAM
IS61NLF102418 STATE BUS SRAM
IS61NLF102436A 36Mb STATE BUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A  1M x 36 and 2M x 18 36Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEBRUARY 2012 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP package • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.