Datasheet Summary
IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A
1M x 36 and 2M x 18 36Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
FEBRUARY 2012
Features
- 100 percent bus utilization
- No wait cycles between Read and Write
- Internal self-timed write cycle
- Individual Byte Write Control
- Single Read/Write control pin
- Clock controlled, registered address, data and control
- Interleaved or linear burst sequence control us- ing MODE input
- Three chip enables for simple depth expansion and address pipelining
- Power Down mode
- mon data inputs and data outputs
- CKE pin to enable clock and suspend operation
- JEDEC 100-pin TQFP package
- Power supply:
NVF: Vdd 2.5V (± 5%), Vddq 2.5V (±...