IS61NVVP51236 Datasheet | ISSI

FEATURES - 100 percent bus utilization - No wait cycles between Read and Write - Internal self-timed write cycle .. - Individual ISSI ADVANCE INFORMATION JULY 2002 DESCRIPTION ® Byte Write Control - Single R/W (Read/Write) control pin - Clock controlled, registered address, data and control - Interleaved or linear burst sequence control using MODE input - Power Down mode - mon data inputs and data outputs - CKE pin to enable clock and suspend operation - JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages - Single +1.8V (± 5%) power supply - JTAG Boundary Scan - Industrial temperature available The 16 Meg 'NVVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and munications customers. They are organized as 256K words by 72 bits, 512K words by 36 bits and are fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature , wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst...