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IS61NVVP51236 - (IS61NVVP25672 / IS61NVVP51236) STATE BUS SRAM

Download the IS61NVVP51236 datasheet PDF. This datasheet also covers the IS61NVVP25672 variant, as both devices belong to the same (is61nvvp25672 / is61nvvp51236) state bus sram family and are provided as variant models within a single manufacturer datasheet.

General Description

® Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Power Down mode Common data inputs and data outputs CKE pin to

Key Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle www. DataSheet4U. com.
  • Individual ISSI.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61NVVP25672_ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
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IS61NVVF204836B FLOW THROUGH (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NVVF409618B FLOW THROUGH (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NVF102418 STATE BUS SRAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NVVP51236B 18Mb STATE BUS SYNCHRONOUS SRAM
IS61NVVP51232B 18Mb STATE BUS SYNCHRONOUS SRAM
IS61NVVP102418B 18Mb STATE BUS SYNCHRONOUS SRAM
IS61NVVP25672 (IS61NVVP25672 / IS61NVVP51236) STATE BUS SRAM
IS61NVF102436A 36Mb STATE BUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61NVVP25672 IS61NVVP51236 256K x 72 and 512K x 36, 18Mb PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle www.DataSheet4U.com • Individual ISSI ADVANCE INFORMATION JULY 2002 DESCRIPTION ® Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages • Single +1.