IS61QDB22M18C - 36Mb QUAD Synchronous SRAM

memory (SRAM) devices.

eliminating the need for high-speed bus turnaround.

all internal operations are self-timed.

• 1Mx36 and 2Mx18 configuration available.
• On-chip Delay-Locked Loop (DLL) for wide data valid window.
• Separate independent read and write ports with concurrent read and write operations.
• Synchronous pipeline read with EARLY write operation.
• Double Data Rate (DDR) interface for read and write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K#) for address and control registering at rising edge.