IS61QDB41M18A Overview
OCTOBER 2014 512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked loop (DLL) for wide data valid window. Separate independent read and write ports with concurrent read and write operations.
IS61QDB41M18A Key Features
- 512Kx36 and 1Mx18 configuration available
- On-chip Delay-Locked loop (DLL) for wide data valid
- Separate independent read and write ports with concurrent read and write operations
- Synchronous pipeline read with late write operation
- Double Data Rate (DDR) interface for read and write input ports
- 1.5 cycle read latency
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control
- Two output clocks (C and C#) for data output control