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IS61QDB42M18A - 36Mb QUAD SYNCHRONOUS SRAM

General Description

APRIL 2016

1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDB42M18 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs
IS61QDB42M36 QUAD (Burst of 4) Synchronous SRAMs
IS61QDB42M36A 72Mb QUAD (Burst 4) SYNCHRONOUS SRAM
IS61QDB42M36C 72Mb QUAD SYNCHRONOUS SRAM
IS61QDB41M18A 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61QDB42M18A IS61QDB41M36A 2Mx18, 1Mx36 36Mb QUAD (Burst 4) SYNCHRONOUS SRAM FEATURES DESCRIPTION APRIL 2016  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  1.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.