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IS61QDB44M18C - 72Mb QUAD SYNCHRONOUS SRAM

General Description

APRIL 2018

2Mx36 and 4Mx18 configuration available.

concurrent read and write operations.

Max.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interface for rea

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IS61QDB44M18C IS61QDB42M36C 4Mx18, 2Mx36 72Mb QUAD (Burst 4) SYNCHRONOUS SRAM FEATURES DESCRIPTION APRIL 2018  2Mx36 and 4Mx18 configuration available.  Separate independent read and write ports with concurrent read and write operations.  Max. 400 MHz clock for high bandwidth  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  1.5 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.