IS61QDB44M18C Datasheet | ISSI

FEATURES DESCRIPTION APRIL 2018 - 2Mx36 and 4Mx18 configuration available. - Separate independent read and write ports with concurrent read and write operations. - Max. 400 MHz clock for high bandwidth - Synchronous pipeline read with late write operation. - Double Data Rate (DDR) interface for read and write input ports. - 1.5 cycle read latency. - Fixed 4-bit burst for read and write operations. - Clock stop support. - Two input clocks (K and K#) for address and control registering at rising edges only. - Two output clocks (C and C#) for data output control. - Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. - +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. - HSTL input and output interface. - Full data coherency. - On-chip Delay-Locked Loop (DLL) for wide data valid window. - Boundary scan using limited set of JTAG 1149.1 functions. - Byte write capability. - Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array - Programmable impedance output drivers via 5x user-supplied precision resistor. The 72Mb IS61QDB42M36C and IS61QDB44M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUAD (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write mand signal, and the second burst is timed to...