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IS61QDP2B21M18A Datasheet 18mb Quadp (burst 2) Synchronous Sram

Manufacturer: ISSI (now Infineon)

Overview: IS61QDP2B21M18A/A1/A2 IS61QDP2B251236A/A1/A2 1Mx18, 512Kx36 18Mb QUADP (Burst 2) Synchronous SRAM (2.

General Description

at page 6 for each ODT option.

DESCRIPTION The and are synchronous, high- performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Key Features

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • 2.0 Cycle read latency.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and co.

IS61QDP2B21M18A Distributor