IS61QDP2B21M36A - 36Mb QUADP (Burst 2) Synchronous SRAM

This page provides the datasheet information for the IS61QDP2B21M36A, a member of the IS61QDP2B22M18A 36Mb QUADP (Burst 2) Synchronous SRAM family.

Product Overview

ISSI

Part number	IS61QDP2B21M36A
Manufacturer	ISSI
File Size	660.37 KB
Description	36Mb QUADP (Burst 2) Synchronous SRAM
Datasheet	IS61QDP2B21M36A Datasheet
Additional preview pages of the IS61QDP2B21M36A datasheet.

devices.

need for high-speed bus turnaround.

operations are self-timed.

1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.0 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and cont.

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Published: Jun 10, 2016 |