IS61QDPB44M18C
Overview
- 2Mx36 and 4Mx18 configuration available.
- Separate independent read and write ports with concurrent read and write operations.
- Max. 567 MHz clock for high bandwidth
- Double Data Rate (DDR) interface for read and write input ports.
- 2.5 cycle read latency.
- Fixed 4-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.
