Datasheet Details
| Part number | IS61QDPB44M18C |
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| Manufacturer | ISSI (now Infineon) |
| File Size | 897.16 KB |
| Description | 72Mb QUADP SYNCHRONOUS SRAM |
| Datasheet |
 IS61QDPB44M18C Datasheet
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General Description
The 72Mb IS61QDPB42M36C/C1/C2 and IS61QDPB44M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices.
These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
Key Features
- 2Mx36 and 4Mx18 configuration available.
- Separate independent read and write ports with concurrent read and write operations.
- Max. 567 MHz clock for high bandwidth.
- Double Data Rate (DDR) interface for read and write input ports.
- 2.5 cycle read latency.
- Fixed 4-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.