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IS66WVE4M16ECLL - 64Mb Async/Page PSRAM

Download the IS66WVE4M16ECLL datasheet PDF. This datasheet also covers the IS66WVE4M16EALL variant, as both devices belong to the same 64mb async/page psram family and are provided as variant models within a single manufacturer datasheet.

General Description

PSRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications.

The 64Mb DRAM core device is organized as 4 Meg x 16 bits.

Key Features

  • Asynchronous and page mode interface.
  • Dual voltage rails for optional performance.
  • ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V.
  • BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V.
  • CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V.
  • Page mode read access.
  • Interpage Read access : 55ns, 70ns.
  • Intrapage Read access : 20ns.
  • Low Power Consumption.
  • Asynchronous Operation < 30 mA.
  • Intrapage Read < 23mA.
  • Standby < 200 uA (max. ).
  • Deep power-down (DPD).
  • ALL/CLL: < 3µA (Typ.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS66WVE4M16EALL-ISSI.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS66WVE4M16EALL 64Mb Async/Page PSRAM
IS66WVE4M16EBLL 64Mb Async/Page PSRAM
IS66WVE4M16ALL 1.8V Core Async/Page PSRAM
IS66WVE4M16BLL 3.0V Core Async/Page PSRAM
IS66WVE4M16TALL 64Mb Async/Page PSRAM
IS66WVE4M16TBLL 64Mb Async/Page PSRAM
IS66WVE4M16TCLL 64Mb Async/Page PSRAM
IS66WVE1M16ALL 1.8V Core Async/Page PSRAM
IS66WVE1M16BLL 3.0V Core Async/Page PSRAM
IS66WVE1M16EALL 16Mb Async/Page PSRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS66WVE4M16EALL/BLL/CLL IS67WVE4M16EALL/BLL/CLL 64Mb Async/Page PSRAM PRELIMINARY INFORMATION Overview The IS66/67WVE4M16EALL/BLL/CLL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. Features  Asynchronous and page mode interface  Dual voltage rails for optional performance  ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V  BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V  CLL: VDD 1.7V~1.