IXTH30N50 Overview
Key Features
- Low R HDMOSTM process DS (on)
- Rugged polysilicon gate cell structure
- VDSS VGS = 0 V TJ = 25°C TJ = 125°C VGS = 10 V, ID = 0.5
- ID25 30N50 Pulse test, t ≤ 300 µs, duty cycle d ≤ 2 % 500 V .087 %/k 2 -0.25 4V %/k ±100 nA 200 µA 3 mA 0.17 Ω
