180N10 Description
100 V 2.0 4.0 V ±100 nA TJ = 25°C T J = 125°C 100 mA 2 mA 8 mW ISOPLUS 247TM G D Isolated back surface G = Gate S = Source D = Drain Patent pending.
180N10 Key Features
- Silicon chip on Direct-Copper-Bond substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
- Low drain to tab capacitance(<25pF)
- Low RDS (on) HDMOSTM process
- Rugged polysilicon gate cell structure
- Unclamped Inductive Switching (UIS)
- Fast intrinsic Rectifier