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S25FL128L Datasheet PDF

Infineon Technologies S25FL128L

The FL-L family devices are flash non-volatile memory products using: • Floating gate technology • 65-nm process lithography The FL-L family connects to a host system via a serial peripheral interface (SPI). The architecture features a page programming buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.
Part No. S25FL128L
Datasheet S25FL128L Download
Manufacturer
Infineon Technologies
Description FL-L flash
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S25FL128L datasheet page 1 preview

FEATURES

● SPI with multi-I/O - Clock polarity and phase modes 0 and 3 - Double data rate (DDR) option - Quad peripheral interface (QPI) option - Extended addressing: 24- or 32-bit address options - Serial command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families - Multi I/O command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families
● Read - Commands: normal, fast, dual I/O, Quad I/O, dualO, QuadO, DDR Quad I/O. - Modes: Burst wrap, continuous (XIP), QPI - Serial flash discoverable parameters (SFDP) for configuration information.
● Program architecture - 256 bytes page programming buffer - 256 Mb (32 MB)/128 Mb (16 MB), 3.0 V FL-L flash memory - Program suspend and resume
● Erase architecture - Uniform 4 KB sector erase - Uniform 32 KB half block erase - Uniform 64 KB block erase - Chip erase - Erase suspend and resume
● 100,000 program/erase cycles, minimum
● 20 year data retention, minimum Datasheet Please re...
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