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S25FL128L - 3.0V FL-L Flash Memory

Download the S25FL128L datasheet PDF. This datasheet also covers the S25FL256L variant, as both devices belong to the same 3.0v fl-l flash memory family and are provided as variant models within a single manufacturer datasheet.

General Description

The Cypress FL-L Family devices are Flash non-volatile memory products using: Floating Gate technology

The FL-L family connects to a host system via a Serial Peripheral Interface (SPI).

Key Features

  • a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can ma.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (S25FL256L-Cypress.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
S25FL128L FL-L flash Infineon
S25FL128K 128-Mbit CMOS 3.0 Volt Flash Memory SPANSION
S25FL128P 128-Mb 3.0 V Flash Memory Cypress Semiconductor
S25FL128P 128 Megabit CMOS 3.0 Volt Flash Memory SPANSION
S25FL128S Flash Non-Volatile Memory CMOS Core SPANSION

Other Datasheets by Cypress (now Infineon)

Part Number Description
S25FL128S 3.0V SPI Flash Memory
S25FL032P 32-Mbit 3.0 V Flash Memory
S25FL064L 64-Mbit (8-Mbyte) 3.0V FL-L SPI Flash Memory
S25FL064P 64-Mbit 3.0 V SPI Flash Memory
S25FL216K 16-Mbit 3.0 V Serial Flash Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
S25FL256L/S25FL128L 256Mbit (32Mbyte)/128Mbit (16Mbyte), 3.0 V FL-L Flash Memory General Description The Cypress FL-L Family devices are Flash non-volatile memory products using: – Floating Gate technology – 65 nm process lithography The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.