Description
The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation.
Features
- Pin-selectable PLL divider ratios support forward
and inverse FEC ratio translation, including:.
- 255/238 (OTU1) Mapping and 238/255 De-mapping.
- 255/237 (OTU2) Mapping and 237/255 De-mapping.
- 255/236 (OTU3) Mapping and 236/255 De-mapping
Example I/O Clock Frequency Combinations Using M2006-02/-12-622.0800 and Inverse FEC Ratios
FEC PLL Ratio Mfec / Rfec 1/1 238/255 237/255 236/255 Base Input Rate 1 (MHz) 622.0800 666.5143 669.3266 672.1627 Output Clock (eithe.
M2006-02 Datasheet
