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M2006-02 - VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION

General Description

The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation.

Key Features

  • Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including:.
  • 255/238 (OTU1) Mapping and 238/255 De-mapping.
  • 255/237 (OTU2) Mapping and 237/255 De-mapping.
  • 255/236 (OTU3) Mapping and 236/255 De-mapping Example I/O Clock Frequency Combinations Using M2006-02/-12-622.0800 and Inverse FEC Ratios FEC PLL Ratio Mfec / Rfec 1/1 238/255 237/255 236/255 Base Input Rate 1 (MHz) 622.0800 666.5143 669.3266 672.1627 Output Clock (eithe.

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Datasheet Details

Part number M2006-02
Manufacturer Integrated Circuit Solution Inc
File Size 83.76 KB
Description VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION
Datasheet download datasheet M2006-02 Datasheet

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M2006-12 VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Integrated Circuit Systems, Inc. Product Brief M2006-02/-12 VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION PIN ASSIGNMENT (9 x 9 mm SMT) FIN_SEL1 GND FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 VCC DNC DNC DNC NC or APC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC GENERAL DESCRIPTION The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming look-up tables. The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection.