IC41LV16257S Datasheet | Integrated Circuit Solution

IC41C16257/IC41C16257S IC41LV16257/IC41LV16257S .. Document Title 256Kx16 bit Dynamic RAM with Fast Page Mode Revision History Revision No 0A History Initial Draft Draft Date August 11,2001 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR021-0A 08/11/2001 IC41C16257/IC41C16257S IC41LV16257/IC41LV16257S .. 256K x 16 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE Features - - - - - - - DESCRIPTION - - The ICSI IC41C16257 and the IC41LV16257 are 262,144 Fast access and cycle time x 16-bit high-performance CMOS Dynamic Random Access TTL patible inputs and outputs Memory. Fast Page Mode allows 512 random accesses Refresh Interval: 512 cycles/8 ms within a single row with access cycle time as short as 12 ns per 16-bit word. The Byte Write control, of upper and lower Refresh Mode: RAS-Only, CAS-before-RAS byte, makes these devices ideal for use in 16-, 32-bit wide (CBR), Hidden data bus systems. Self Refresh Mode: 512 cycles/64 ms (S version These Features make the IC41C16257 and the IC41LV16257 only) ideally suited for high band-width graphics, digital signal JEDEC standard pinout processing, high-performance puting systems, and peripheral applications. Single power supply: - 5V ± 10% (IC41C16257) The IC41C16257 and the IC41LV16257 are packaged in a 40-pin, 400mil SOJ and TSOP-2. - 3.3V ± 10% (IC41LV16257) Byte Write and Byte Read operation via KEY TIMING PARAMETERS two CAS Parameter -35 -50 -60 Unit Available in 40-pin SOJ and TSOP-2 Max. RAS Access Time (t RAC) Max. CAS Access Time (t CAC) Max. Column Address Access Time (t AA) Min. Fast Page Mode Cycle Time (t PC) 35 10 18 12 60 50 14 25 20 90 60 15 30 25 110 ns ns ns ns ns PIN CONFIGURATIONS 40-Pin TSOP-2 40-Pin SOJ Min. Read/Write...