ICS650R-07B Datasheet | Integrated Circuit Systems

( Data Sheet : .. ) ICS650-07B Broad Clock Source Description The ICS650-07B is a low cost, low jitter, high performance clock synthesizer customized for Broad. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 25.00 MHz clock or fundamental mode crystal input to produce multiple output clocks of 25.0 MHz, two 125.0 MHz, 133.33 MHz, and a selectable 33.3/66.6 MHz clock. All output clocks are frequency locked together. The ICS650-07B outputs all have 0 ppm synthesis error. Do not use the 125 MHz outputs to drive Gigabit Ethernet SERDES. Instead, the 25 MHz clock can be driven into our ICS601 in the X5 mode. The ICS601 has low enough jitter and phase noise for all popular SERDES. Features - Packaged in 20 pin narrow (150 mil) SSOP (QSOP) - 25.00 MHz fundamental crystal or clock input - Four fixed output clocks of 25 MHz, 133.33 MHz, and two copies of 125 MHz - One selectable output clock of 33.3 or 66.6 MHz - Zero ppm synthesis error in all clocks - PCI clock switching occurs within 1 µs - Ideal for Broad’s BCM5600 chipset - Full CMOS output swing - Advanced, low power, sub-micron CMOS process - 3.0 V to 5.5 V operating voltage Block Diagram VDD GND Output Buffer PCI CLK 125.00 MHz 125.00 MHz 133.33 MHz Clock Synthesis and Control Circuitry Output Buffer Output Buffer 25.00 MHz crystal or clock X1 Clock Buffer/ Crystal Oscillator Output Buffer Output Buffer 25.00 MHz X2 OE (all outputs) Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board). 1 Revision 042600 Printed 11/15/00 Integrated Circuit Systems,...