ICS650R-12 Datasheet | Integrated Circuit Systems

( Data Sheet : .. ) ICS650-12 MPEG Clock Synthesizer Description The ICS650-12 is a low cost, low jitter, high performance clock synthesizer designed to produce fixed clock outputs of 13.5 MHz and 27.0 MHz and four selectable clock outputs of two Processor Clocks (PCLK1 and PCLK2), Audio Clock (ACLK), and munications Clock (CCLK). Using our patented analog Phase Locked Loop (PLL) techniques, the device uses a 27.0 MHz clock or fundamental crystal input to produce clocks ideal for Digital Video/MPEGbased applications. Features - - - - Packaged in 20 pin tiny SSOP (QSOP) Input Frequency of 27.0 MHz Zero ppm synthesis error in output clocks Provides fixed 13.5 MHz and 27.0 MHz. Also provides two selectable Processor Clocks, one Audio Clock, and one munications Clock - Ideal for Digital Video/MPEG-based applications - 3.3 V or 5.0 V operating voltage - Entire chip powers down (when CS1=CS0=0) Block Diagram Output Buffer PS2:0 Clock Synthesis and Control Circuitry Output Buffer Output Buffer Output Buffer Output Buffer ÷2 27.0 MHz crystal or clock Input Buffer/Crystal Oscillator Output Buffer PCLK1 PCLK2 ACLK CCLK AS2:0 CS1:0 13.5 MHz 27.0 MHz 1 Revision 113000 Integrated Circuit Systems, Inc. - 525 Race Street - San Jose - CA- 95126- (408) 295-9800tel - .icst. MDS 650-12 A .. ICS650-12 MPEG Clock Synthesizer Pin Assignment PS2 X2 X1 VDD CS1 GND ACLK PCLK1 CS0 AS2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PS1 PS0 CCLK PCLK2 VDD AS1 GND 13.5M 27M AS0 PCLK1 and PCLK2 Select Table (in MHz) PS2 PS1 PS0 PCLK1 PCLK2 0 0 0 108.00 54.00 0 0 1 55.00 27.5 0 1 0 66.67 33.33 0 1 1 80.00 40.00 1 0 0 54.00 27.00 1 0 1 81.00 40.5 1 1 0 50.00 25.00 1 1 1 60.00 30.00 ACLK Select Table (in MHz) AS2 AS1 AS0 ACLK 0 0 0 12.288 0 0 1 11.2896 0 1 0 8.192 0 1 1 24.576 1 0 0 8.192 1 0 1 16.9344 1 1 0 18.432 1 1 1 11.2896 CCLK Select Table (in MHz) CS1 CS0 CCLK 0 0 All off- 0 1 20.00 1 0 66.6666 1 1 24.576 - Note: Entire chip powers...