ICS83840B Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. DDR SDRAM MUX Features - 40 low skew single-ended DIMM ports - 4 SSTL-2 patible enable inputs - Maximum Switching Speed: 3ns - Output skew: 120ps (maximum) - Bank skew: 60ps (maximum) - ron = 8Ω (typical) - Full 2.5V supply modes - 0°C to 70°C ambient operating temperature - Pin patible with the CBTV4010 GENERAL DESCRIPTION The ICS83840B is a DDR SDRAM MUX and is ICS a member of the Hi Per Clock S™ family of High Hi Per Clock S™ Performance Clock Solutions from ICS. The device has 10 Host Lines and each host line can be passed to 4 Data Ports. The 10 channels are allocated as follows in the DDR SDRAM application: 8 data lines, 1 strobe line and 1 DQm line. The Host/ Data Ports are patible with single-ended SSTL-2 and the device operates from a 2.5V supply. .. Guaranteed low output skew makes the ICS83840B ideal for demanding applications which require well defined performance and repeatability. SIMPLIFIED SCHEMATIC LOGIC DIAGRAM HP0 RON Sw Sw Sw 0DP0 1DP0 2DP0 Sw 3DP0 HPx n DPx 400Ω HP9 RON Sw Sw Sw Sw 0DP9 1DP9 2DP9 3DP9 n Sn SW n S0 n S1 n S2 n S3 PIN ASSIGNMENT 1 A B C D E F G H J K L 2DP9 1DP9 0DP9 1DP8 0DP8 3DP7 VDD n S2 nc 2 n S1 VDD n S3 GND 3DP9 HP9 3DP8 2DP8 HP8 GND 2DP7 3 nc n S0 1DP0 0DP0 2DP0...