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ICS85408 - TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

General Description

The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution HiPerClockS™ Chip and a member of the HiPerClock S ™ family of High Performance Clock Solutions from ICS.

Key Features

  • 8 Differential LVDS outputs.
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
  • Maximum output frequency: 700MHz.
  • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks.
  • Translates any single-ended input signal to LVDS with resistor bias on nCLK input.
  • Multiple output enable inputs for disabling unused outputs in reduced fanout appl.

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Datasheet Details

Part number ICS85408
Manufacturer Integrated Circuit Systems
File Size 206.93 KB
Description TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Datasheet download datasheet ICS85408 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Integrated Circuit Systems, Inc. ICS85408 LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP FEATURES • 8 Differential LVDS outputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks • Translates any single-ended input signal to LVDS with resistor bias on nCLK input • Multiple output enable inputs for disabling unused outputs in reduced fanout applications • Output skew: 50ps (maximum) • Part-to-part skew: 550ps (maximum) • Propagation delay: 2.4ns (maximum) • 3.