ICS9147-01 Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUMTM General Description The ICS9147-01 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel Pentium Pro. Two bidirectional I/O pins (FS1,FS2) are latched at power-on to the functionality table, with FS0 selectable in real-time to toggle between conditions. The inputs provide for tristate and test mode conditions to aid in system level testing. These multiplying factors can be customized for specific applications. Glitch-free stop clockcontrols are provided for CPU clocks and BUS clocks. High drive BUS and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 p F loads. CPU outputs typically provide better than 1V/ns slew rate into 20 p F loads while maintaining 50 ± 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Seperate buffers supply pins VDD2 allow for 3.3V or reduced voltage swing (from 2.9 to 2.5V) for CPU (1:4) and IOAPIC outputs. Features - - - - - - - - - - - - - - Four copies of CPU clock Six SDRAM (3.3 V TTL), usable as AGP clocks Seven copies of BUS clock (synchronous with CPU clock/2 or CPU/2.5 for 75 and 83.3 MHz CPU) CPU clocks to BUS clocks skew 1-4ns (CPU early) One IOAPIC clock @14.31818 MHz Two copies of Ref. clock @14.31818 MHz One each 48/ 24 MHz (3.3 V TTL) This device is configured into the Mobile mode for power management of Intel 430 TX Ref. 14.31818 MHz Xtal oscillator input Separate 66/60 MHz select pin (LSB of select pins) Separate VDD2 for four CPU and single IOAPIC output buffers to allow 2.5V output (or Std. Vdd) Power Management Control Input pins 3.0V - 3.7V supply range w/2.5V patible outputs 48-pin SSOP package Block Diagram Pin Configuration 48-Pin SSOP Pentium is a trademark of Intel Corporation 9147-01Rev B 04/25/01 ICS reserves the right to make changes in the device data identified in this publication without further notice....