ICS9147-14 Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM/Pro TM General Description The ICS9147-14 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel Pentium Pro. Two bidirectional I/O pins (FS1,FS2) are latched at power-on to the functionality table, with FS0 selectable in real-time to toggle between conditions. • • • • • • • • • • • • • • • • • • • • Features High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 p F loads. CPU outputs typically provide better than 1V/ns slew rate into 20 p F loads while maintaining 50 ± 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Seperate buffers supply pins VDDL1 allow for 3.3V or reduced voltage swing (from 2.9 to 2.5V) for CPU (0:3) and IOAPIC outputs. Block Diagram Four copies of CPU clock Twelve SDRAM (3.3V TTL), usable as AGP clocks Seven copies of PCICLK clock (synchronous with CPU clock/2 or CPU/2.5 for 75 and 83.3 MHz CPU) CPU clocks to PCICLK clocks skew 1-4ns, center 2.6ns. One IOAPIC clock @14.31818 MHz Two copies of Ref. clock @14.31818 MHz Ref. 14.31818 MHz Xtal oscillator input Separate VDDL1 for four CPU and single IOAPIC output buffers to allow 2.5V output (or Std. Vdd) One each 48/ 24MHz (3.3V TTL) 3.3V outputs: SDRAM, PCI, REF, 48/24MHz. 2.5V or 3.3V outputs: CPU, IOAPIC. 20 ohm CPU clock output impedance 20 ohm PCI clock output impedance 1.5ns rise time (30 p F loading) ±250 ps CPU, PCI clock skew 350ps (cycle by cycle) CPU jitter 2ms Power up clock stable time 45-55% Clock duty cycle 48 pin 300 mil SSOP package 3.0V – 3.7V supply range w/2.5V patible outputs Pin Configuration Power Groups VDD1 = REF (0:1), X1, X2, 24MHz, 48MHz VDD2 = PCICLKF, PCICLK(0:5) VDD3 = SDRAM (0;11) VDDL1 = CPUCLK (0:3) 9147-14 Rev B 071897P 48-Pin SSOP - Internal Pull-up Resistor of 300K to 3.3V on indicated inputs Pentium is a trademark of Intel Corporation ICS...