ICS9147-06 Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUMTM General Description The ICS9147-06 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel Pentium Pro. Two different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Glitch-free Stop clock control is provided for CPU and BUS clocks. plete chip low current mode is achieved with the Power Down# pin. High drive BUS outputs typically provide greater than 1 V/ ns slew rate into 30 p F loads. CPU outputs typically provide better than 1V/ns slew rate into 20 p F loads while maintaining 50± 5% duty cycle. The REF and IOAPIC clock outputs typically provide better than 0.5V/ns slew rates. Separate buffer supply pins VDDL allow for nominal 3.3V voltage or reduced voltage swing (from 2.9 to 2.5V) for CPU (1:4) and IOAPIC outputs. Features • • • • • • • Generates five processor, eight bus, four 14.31818 MHz, two 48 MHz clocks for USB support and one 24 MHz clock. CPU to BUS clock skew 1 to 4ns (CPU early) Synchronous clocks skew matched to 250ps window on CPU and 500ps window on BUS. Selectable multiplying ratios Glitch free stop clock controls CPUEN and BUSEN 3.0V – 3.7V supply range, 2.5V to VDD supply range for CPU (1:4) clocks and IOAPIC clock. 48-pin SSOP package Pin Configuration Block Diagram 48-Pin SSOP Pentium is a trademark of Intel Corporation 9147- 06 Rev A 5/29/97P ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. Functionality PD# 1 1 1 1 1 1 0 BUSEN 1 1 1 1 1 0 X CPUEN 1 1 1 1 0 1 X FS1 0 0 1 1 X X X FS0 0 1 0 1 X X X CPU (1:4) CPUH Tristate 60 66.6 REF/2 LOW Running LOW BUS Tristate 30 33.3 REF/4 Running LOW LOW REF IOAPIC Tristate...