MK2049-34 - 3.3 V Communications Clock PLL

Product Overview

Integrated Circuit Systems

Part number	MK2049-34
Manufacturer	Integrated Circuit Systems
File Size	135.66 KB
Description	3.3 V Communications Clock PLL
Datasheet	MK2049-34 Datasheet
Additional preview pages of the MK2049-34 datasheet.

The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies.

With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies.

Packaged in 20 pin SOIC.
3.3 V ±5% operation.
Fixed I/O phase relationship on all selections.
Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
Accepts multiple inputs: 8 kHz backplane clock, Loop Timing frequencies, or 10-36 MHz.
Locks to 8 kHz ±100 ppm (External mode).
Buffer Mode allows jitter attenuation of 10.
36 MHz.

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Published: May 7, 2005 |