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MK2049-34 Datasheet 3.3 V Communications Clock Pll

Manufacturer: Integrated Circuit Systems

Overview: MK2049-34 3.3 V Communications Clock PLL.

General Description

The MK2049-34 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies.

With an 8 kHz clock input as a reference, the MK2049-34 generates T1, E1, T3, E3, ISDN, xDSL, and other communications frequencies.

This allows for the generation of clocks frequency-locked and phase-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems.

Key Features

  • Packaged in 20 pin SOIC.
  • 3.3 V ±5% operation.
  • Fixed I/O phase relationship on all selections.
  • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
  • Accepts multiple inputs: 8 kHz backplane clock, Loop Timing frequencies, or 10-36 MHz.
  • Locks to 8 kHz ±100 ppm (External mode).
  • Buffer Mode allows jitter attenuation of 10.
  • 36 MHz.

Similar Datasheet

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MK2049-34 Distributor