IDT72V3642 Datasheet | Integrated Device Tech

3.3 VOLT CMOS Sync Bi FIFOTM 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2 .EATURES: - - IDT72V3622 IDT72V3632 IDT72V3642 - - - - - - - - - Memory storage capacity: IDT72V3622 - 256 x 36 x 2 IDT72V3632 - 512 x 36 x 2 IDT72V3642 - 1,024 x 36 x 2 Supports clock frequencies up to 100 MHz Fast access times of 6.5ns Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering data in opposite directions Mailbox bypass register for each FIFO Programmable Almost-Full and Almost-Empty flags Microprocessor Interface Control Logic FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB - - - Select IDT Standard timing (using EFA, EFB, FFA and FFB flags functions) or First Word Fall Through timing (using ORA, ORB, IRA and IRB flag functions) Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving 120-pin Thin Quad Flatpack (TQFP) Functionally patible to the 5V operating IDT723622/723632/ 723642 Industrial temperature range (- 40οC to +85οC) is available DESCRIPTION: The IDT72V3622/72V3632/72V3642 are functionally patible versions of the IDT723622/723632/723642, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, highspeed, low-power, CMOS Bidirectional Sync FIFO (clocked) memories which support clock frequencies up to 100MHz and have read access times as fast as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. munication between .UNCTIONAL BLOCK DIAGRAM CLKA CSA W/RA ENA MBA Mail 1 Register Input Register RAM ARRAY 256 x 36 512 x 36 1,024 x 36 Output Register Port-A Control Logic MBF1 RST1 FIFO1, Mail1 Reset Logic Write Pointer Read Pointer EFB/ORB AEB FFA/IRA AFA FIFO 1 Status Flag Logic FS0 FS1 A0 - A35 Programmable Flag Offset...