IDT72V3664 Datasheet | Integrated Device Tech

3.3 VOLT CMOS Sync Bi FIFOTM WITH BUS-MATCHING 4,096 x 36 x 2 Features - Memory storage capacity: - 4,096 x 36 x 2 - Clock frequencies up to 100 MHz (6.5ns access time) - Two independent clocked FIFOs buffering data in opposite directions - Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRB flag functions) - Programmable Almost-Empty and Almost-Full flags; each has five default offsets (8, 16, 64, 256 and 1,024 ) - Serial or parallel programming of partial flags - Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits (byte) - Big- or Little-Endian format for word and byte bus sizes - Retransmit Capability - Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings - Mailbox bypass registers for each FIFO - Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading...