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ICS831724I - Differential Clock/Data Multiplexer

General Description

The ICS831724I is a high-performance, differential HCSL clock/data multiplexer and fanout buffer.

The device is designed for the multiplexing and fanout of high-frequency clock and data signals.

The device has two differential, selectable clock/data inputs.

Key Features

  • 2:1 differential clock/data multiplexer with fanout.
  • Two selectable, differential inputs.
  • Each differential input pair can accept the following levels: HCSL, LVDS, LVPECL.
  • Four differential HCSL outputs.
  • Maximum input/output clock frequency: 350MHz.
  • Maximum input/output data rate: 700Mb/s (NRZ).
  • LVCMOS interface levels for all control inputs.
  • PCI Express Gen 1,2,3 jitter compliant.
  • Input skew: 165ps (maximum).

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Datasheet Details

Part number ICS831724I
Manufacturer Integrated Device Technology
File Size 524.04 KB
Description Differential Clock/Data Multiplexer
Datasheet download datasheet ICS831724I Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Differential Clock/Data Multiplexer ICS831724I DATA SHEET General Description The ICS831724I is a high-performance, differential HCSL clock/data multiplexer and fanout buffer. The device is designed for the multiplexing and fanout of high-frequency clock and data signals. The device has two differential, selectable clock/data inputs. The selected input signal is distributed to four low-skew differential HCSL outputs. Each input pair accepts HCSL, LVDS and LVPECL levels. The ICS831724I is characterized to operate from a 3.3V power supply. Guaranteed input, output-to-output and part-to-part skew characteristics make the ICS831724I ideal for those clock and data distribution applications demanding well-defined performance and repeatability.