Datasheet4U Logo Datasheet4U.com

ICS831752I - Clock Switch

General Description

The ICS831752I is a high-performance, differential HCSL clock switch.

The device is designed for the routing of PCIe clock signals in ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen 3.

Key Features

  • Clock switch for PCIe and ATCA/AMC.

📥 Download Datasheet

Datasheet Details

Part number ICS831752I
Manufacturer Integrated Device Technology
File Size 849.41 KB
Description Clock Switch
Datasheet download datasheet ICS831752I Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ICS831721I Differential Clock/Data Multiplexer Renesas
ICS831721I Differential Clock/Data Multiplexer IDT
ICS83115BRLFT LOW SKEW/ 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER Integrated Circuit Systems
ICS83115BRT LOW SKEW/ 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER Integrated Circuit Systems
ICS8312 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER Integrated Circuit Systems

Other Datasheets by Integrated Device Technology

Part Number Description
ICS831724I Differential Clock/Data Multiplexer
ICS831742I 4:2 Differential Clock/Data Multiplexer
ICS8312 1-TO-12 LVCMOS/LVTTL FANOUT BUFFER
ICS83023I 1-TO-1 DIFFERENTIAL-TOLVCMOS TRANSLATOR/BUFFER
ICS83026I-01 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Clock Switch for ATCA/AMC and PCIe Applications ICS831752I DATA SHEET General Description The ICS831752I is a high-performance, differential HCSL clock switch. The device is designed for the routing of PCIe clock signals in ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen 3. The device has one differential, bi-directional I/O (FCLK) for connection to ATCA clock sources and to clock receivers through a connector. The differential clock input CLK is the local clock input and the HCSL output Q is the local clock output. In the common clock mode, FCLK serves as an input and is routed to the differential HCSL output Q. There are two local clock modes. In the local clock mode 0, CLK is the input, Q is the clock output and FCLK is in high-impedance state.