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IDT71V632 - 64K x 32 3.3V Synchronous SRAM

This page provides the datasheet information for the IDT71V632, a member of the IDT-71V 64K x 32 3.3V Synchronous SRAM family.

Datasheet Summary

Description

with full support of the Pentium™ and PowerPC™ processor interfaces.

The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz.

Features

  • x x IDT71V632 x x x x x x 64K x 32 memory configuration Supports high system speed: Commercial:.
  • A4 4.5ns clock access time (117 MHz) Commercial and Industrial:.
  • 5 5ns clock access time (100 MHz).
  • 6 6ns clock access time (83 MHz).
  • 7 7ns clock access time (66 MHz) Single-cycle deselect functionality (Compatible with Micron Part # MT58LC64K32D7LG-XX) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), by.

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Datasheet Details

Part number IDT71V632
Manufacturer Integrated Device Technology
File Size 823.39 KB
Description 64K x 32 3.3V Synchronous SRAM
Datasheet download datasheet IDT71V632 Datasheet
Additional preview pages of the IDT71V632 datasheet.

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Full PDF Text Transcription

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64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect Features x x IDT71V632 x x x x x x 64K x 32 memory configuration Supports high system speed: Commercial: – A4 4.5ns clock access time (117 MHz) Commercial and Industrial: – 5 5ns clock access time (100 MHz) – 6 6ns clock access time (83 MHz) – 7 7ns clock access time (66 MHz) Single-cycle deselect functionality (Compatible with Micron Part # MT58LC64K32D7LG-XX) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) Power down controlled by ZZ input Operates with a single 3.3V power supply (+10/-5%) Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP).
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