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IDT71V67802 - 3.3V Synchronous SRAMs

This page provides the datasheet information for the IDT71V67802, a member of the IDT-71V 3.3V Synchronous SRAMs family.

Datasheet Summary

Description

The IDT71V67602/7802 are high-speed SRAMs organized as 256K x 36/512K x 18.

The IDT71V676/78 SRAMs contain write, data, address and control registers.

Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.

Features

  • 256K x 36, 512K x 18 memory configurations Supports high system speed:.
  • 166MHz 3.5ns clock access time.
  • 150MHz 3.8ns clock access time.
  • 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 1.

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Datasheet Details

Part number IDT71V67802
Manufacturer Integrated Device Technology
File Size 355.19 KB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet IDT71V67802 Datasheet
Additional preview pages of the IDT71V67802 datasheet.

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Full PDF Text Transcription

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256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect x x IDT71V67602 IDT71V67802 Features 256K x 36, 512K x 18 memory configurations Supports high system speed: – 166MHz 3.5ns clock access time – 150MHz 3.8ns clock access time – 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array. Description The IDT71V67602/7802 are high-speed SRAMs organized as 256K x 36/512K x 18.
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